A semiconductor device may include discrete devices such as a capacitor, a transistor, etc. The transistor may include a gate pattern on a semiconductor substrate and impurity regions disposed in the semiconductor substrate, which overlap the gate pattern. The impurity regions and the gate pattern determine the electrical characteristics of the transistor when the semiconductor device is driven. The impurity regions are referred to as source and drain regions of the transistor. The gate pattern is formed using at least one conductive layer. The conductive layer may be formed using a doped polysilicon layer.
The conductive layer may cause a parasitic capacitor to be formed in the semiconductor substrate while the transistor is driven. The parasitic capacitor is formed by diffusion of impurity ions into the conductive layer. A capacitance of the parasitic capacitor makes it difficult to transfer a voltage applied to the gate pattern to the semiconductor substrate within a desired time. In particular, the parasitic capacitor may cause a voltage drop corresponding to the capacitance to deteriorate the drivability of the transistor. Therefore, it is typically necessary for the gate pattern to suppress diffusion of the impurity ions in the conductive layer while the transistor is driven.
U.S. Pat. No. 6,204,103 to Lars W. Liebmann, Gang Bai, et al (the '103 patent) discloses a process to make complementary silicide metal gates for CMOS technology. According to the '103 patent, the process includes forming an insulating layer between first and second MOSFETs (metal oxide semiconductor field effect transistors). A first metal layer is formed on a gate of the first MOSFET. Then, a second metal layer is formed on a gate of the second MOSFET. The first metal layer reacts with polysilicon composing the gate of the first MOSFET to form a first silicide region. The second metal layer reacts with polysilicon composing the gate of the second MOSFET to form a second silicide region. However, it is difficult for the process to stably form the first and second silicide regions on the entire surface of the semiconductor substrate, since the first and second metal layers may insufficiently react with the polysilicon composing the gates of the first and second MOSFETs.